1. Technical Field
Embodiments of the invention relate to semiconductor devices controlling a precharge operation and semiconductor systems including the same.
2. Related Art
Semiconductor devices may receive or output data through input/output (I/O) lines. Signals of the I/O lines may be sensed and amplified during a read operation or a write operation, and the I/O lines may be precharged before commands are applied to the I/O lines. The term “precharge” means that signal lines such as the I/O lines are driven to a predetermined voltage level before data or signals are applied to the I/O lines in order to improve an operation speed of a semiconductor device while the data or the signals are inputted to or outputted from the semiconductor device. In addition, the precharging may include a precharge operation which is performed in accordance with an external precharge signal and an auto-precharge operation which is automatically performed after a command for a read operation or a write operation is inputted to a semiconductor device.
Meanwhile, the semiconductor device may receive data and a command (or a control signal) for controlling the input or output of the data from an external device to operate. In such a case, the semiconductor device is not able to output the data immediately at a point of time that a command for a read operation is inputted to the semiconductor device. That is, since an internal operation for outputting the data is performed in the semiconductor device after the command for the read operation is applied to the semiconductor device, a standby time may be required to output the data from the semiconductor device. Hence, the standby time extending from a point of time that the command (or a control signal) is applied to the semiconductor device till a point of time that the internal operation terminates is referred to as “latency”.
For example, the latency, which is defined in the specification for semiconductor devices, may include column address strobe (CAS) latency (CL), CAS write latency (CWL) and additive latency (AL). The CL may correspond to a standby time (or a time interval) from a moment that a read command is applied to a semiconductor device till a moment that data are outputted from the semiconductor device through data pins. The CWL may correspond to a standby time (or a time interval) from a moment that a write command is applied to a semiconductor device till a moment that data corresponding to the write command are inputted to the semiconductor device. The AL may correspond to a standby time (or a time interval) from a moment that a row address is inputted to a semiconductor device till a moment that a column address is inputted to the semiconductor device during a read operation or a write operation.
The latencies may be stored in a mode register set (MRS) included in a semiconductor device, and the semiconductor device may operate based on information on the latencies which are stored in the MRS.